Semiconductor storage device

ABSTRACT

There is provided a semiconductor storage device capable of executing a high-speed read operation without increasing a chip area thereof. The semiconductor storage device includes per-bit sensing circuits  103  each connected to a pair of bit lines (BLT, BLN) and a data output circuit  104  connected to the bit lines BLT from the per-bit sensing circuits, for outputting read data. Each of the per-bit sensing circuits  103  includes a pre-charge circuit for setting the bit line pair to a supply voltage VDD when a bit line pair selection signal YS is inactive, a latch circuit for setting the bit line pair to complementary levels (VDD and GND) according to a read signal when the bit line pair selection signal YS and a sensing circuit activation signal SE are active, and a data write circuit connected to a pair of write data lines (WDT, WDN), for setting one of the bit line pair to a second level (GND) according to write data when the bit line pair selection signal is active. The data output circuit  104  includes a logic circuit and an output transistor. The logic circuit outputs a first value when the bit lines are all at a first level (VDD) and outputs a second value when at least one of the bit lines is at the second level. The output transistor outputs read data to a data output line DL based on an output of the logic circuit.

This application claims priority from PCT Application No.PCT/JP2004/012368 filed Aug. 27, 2004 and from Japanese Application No.2003-3 13056 filed Sep. 4, 2003, which applications are incorporatedherein by reference.

TECHNICAL FIELD

The present invention relates to a semiconductor storage device. Morespecifically, the invention relates to a configuration of a sensingcircuit suitable for being applied to a static random access memory forwhich an ultra-high speed operation is required, and the semiconductorstorage device including the sensing circuit.

BACKGROUND ART

In custom ICs such as an ASIC (Application Specific Integrated Circuit)or the like, improvement in an operating speed is realized by transistorfiner geometries. A gate delay time t is formulated as shown in thefollowing expression (1), using a capacitance C, a voltage V, and acurrent I. That is, the gate delay time is proportional to a valueobtained by dividing electric charge accumulated in the capacitance(=the capacitance C×the voltage V) by the current I.t∝C·V/I  (1)

When finer device geometries are achieved (e.g. when a channel length ora gate oxidization film thickness is reduced), each parameter of thecapacitance, voltage, or current is reduced to 1/K according to ascaling rule (a proportional reduction rule). Thus, likewise, the gatedelay time t can also be reduced to 1/K.

On the other hand, SRAMs (static random access memories) cannot reducethe delay time to 1/K just by achieving the finer device geometries. Thefollowing is a description about this.

A bit line delay time t_(b1), which constitutes a lot in the delay timeof the SRAM can be formulated as in the following expression (2) using abit line capacitance C_(b1), a potential difference between a bit linepair ΔV_(b1), and a cell current I_(cell).t _(b1) =C _(b1) ·ΔV _(b1) /I _(cell)  (2)

With achievement of the finer geometries, the capacitance C_(b1) and thecell current I_(cell) can be reduced to 1/K according to the scalingrule (proportional reduction rule). On contrast therewith, the potentialdifference between a bit line pair ΔV_(b1) is a parameter determined byan offset voltage of a sense amplifier, and cannot be reduced withachievement of the finer geometries. Accordingly, the bit line delaytime t_(b1) cannot be reduced to 1/K with achievement of the finergeometries.

As described above, a higher-speed operation of the SRAM cannot beperformed just by achieving the transistor finer geometries. For thisreason, in the conventional SRAM, by changing a memory configuration,the higher speed is achieved (refer to Non-patent Document 1, forexample). When the number of cells per bit line is reduced to a half,the bit line capacitance C_(b1) is also almost halved. As a result,according to the above expression (2), the bit line delay time t_(b1) isalso likewise almost halved.

However, this design method increases the number of banks and the numberof sensing circuits.

FIG. 8 is a diagram showing a typical configuration example of aconventional sensing circuit. Referring to FIG. 8, a memory cell array801 includes memory cells arranged at intersections between a pluralityof word lines not shown and a plurality of bit line pairs. A memory cellincludes a flip-flop and two pass transistors (also referred to as“access transistors”). The flip-flop is constituted by cross-connectinginputs and outputs of two inverters. The two pass transistors areconnected between a connecting node of the inputs and the outputs of thetwo inverters and respective bit lines of a bit line pair. Gates of thetwo pass transistors are connected in common to a word line.

Referring to FIG. 8, a bit line pair selection circuit 802 includes apMOS transistor P101 with a source thereof connected to a power supplyVDD and a drain thereof connected to a bit line BLT, a PMOS transistorP102 connected between a pair of the bit line BLT and a bit line BLN,and a PMOS transistor P103 with a source thereof connected to the powersupply VDD and a drain thereof connected to the bit line BLN. Gates ofthe pMOS transistors P101, P102, and P103 are connected in common to apre-charge control signal PC.

The bit line pair selection circuit 802 further includes an nMOStransistor N101, an nMOS transistor N102, an NOR circuit 811, a pMOStransistor P104, and a pMOS transistor P105. The nMOS transistor N101 isconnected between the bit line BLT and a write data signal line WDT,which is one of a pair of the write data signal line WDT and a writedata signal line WDN. The nMOS transistor N102 is connected between theother write data signal line WDN of the write data signal line pair andthe bit line BLN. Two input terminals of the NOR circuit 811 areconnected to a write control signal (write enable signal)/WE and a bitline pair selection signal /YS (also referred to as a “column selectionsignal”), and an output terminal of the NOR circuit 811 is connected incommon to gates of the nMOS transistors N101 and N102. The pMOStransistor P104 is connected between a node SAT of a sense amplifier 803and the bit line BLT. The pMOS transistor P105 is connected between anode SAN of the sense amplifier 803 and the bit line BLN. Gates of thepMOS transistors P104 and P105 are connected in common to the bit linepair selection signal /YS. The write control signal /WE and the bit linepair selection signal /YS become active at low levels thereof (of aground potential GND). The bit line pair selection signal /YS is outputfrom a column decoder not shown (for decoding a column address andselecting a bit line pair corresponding to the address).

Referring to FIG. 8, the sense amplifier 803 includes a pMOS transistorP204 with a source thereof connected to the power supply VDD and a drainthereof connected to the node SAT, a pMOS transistor P205 with a sourcethereof connected to the power supply VDD and a drain thereof connectedto the node SAN, and a pMOS transistor P203 connected between the nodesSAT and SAN. Gates of the pMOS transistors P203, P204, and P205 areconnected in common to a control signal RSE. Before or after read andwrite operations, the control signal RSE is driven low, and the nodesSAT and SAN are both set to the power supply voltage VDD. The senseamplifier 803 includes a pMOS transistor P201 with a source thereofconnected to the power supply VDD and a drain thereof connected to thenode SAT, a pMOS transistor P202 with a source thereof connected to thepower supply VDD and a drain thereof connected to the node SAN, and nMOStransistors N201 and N202 with drains thereof connected to the node SATand the node SAN, respectively, and sources thereof connected in common.Gates of the pMOS transistor P201 and the nMOS transistor N201 areconnected in common to the node SAN. The gates of the pMOS transistorP201 and the nMOS transistor N201 are connected in common to the nodeSAN.

The sense amplifier 803 further includes an nMOS transistor N203 with adrain thereof connected to a common connecting node between the sourcesof the nMOS transistors N201 and N202 and an nMOS transistor N204 with adrain thereof connected to a source of the nMOS transistor N203, and asource thereof connected to the potential GND of a substrate. A gate ofthe nMOS transistor N203 is connected to a sense amplifier activationsignal SAE (that is set to the power-supply potential of the powersupply VDD when the sense amplifier 803 is activated). A gate of thenMOS transistor N204 is connected to the control signal RSE. The nodeSAT is connected to an input terminal of an inverter 812. An outputterminal of the inverter 812 is connected to a gate of an nMOStransistor N205 with a drain thereof connected to a data output line DLand a source thereof grounded (or set to the substrate potential GND).The node SAN is connected to an input terminal of an inverter 813. Whenthe sense amplifier activation signal SAE is set to the power supplyvoltage VDD and when the sense amplifier 803 is activated, the pMOStransistors P201 and P202, nMOS transistors N201 and N202 constitute alatch circuit. Then, an amplification operation as follows is performed:through an on-state transistor of the pMOS transistors P201 and 202 (thetransistor with a gate thereof connected to one of the nodes SAT and SANon a lower voltage side), the node on a higher voltage side is chargedto the power supply voltage VDD. Through an on-state transistor of thenMOS transistors N201 and N202 (the transistor with a gate thereofconnected to one of the nodes SAT and SAN on the higher voltage side),the node on the lower voltage side is discharged to the substratepotential GND.

When a read operation is performed, data stored in a selected memorycell (not shown) in the memory cell array 801 is output to a bit linepair BLT and BLN to which the selected memory cell is connected, and thepotential difference ΔV_(b1) is generated between the bit line pair BLTand BLN after a certain time. In the bit line pair selection circuit802, the bit line pair selection signal /YS is set to a low level (orthe substrate potential GND), the pMOS transistors P104 and P105 areturned on, and the potential difference ΔV_(b1) between the selected thebit line pair BLT and BLN is transferred to the nodes SAT and SAN in thesense amplifier 803.

When the sense amplifier activation signal SAE is set to a high level(or the power supply voltage VDD), the sense amplifier 803 amplifies thepotential difference ΔV_(b1) between the nodes SAT and SAN and outputsread data to the data output line DL. When the node SAT is at thesubstrate potential GND, an nMOS transistor N205 that receives an outputof the inverter 812 (at the power supply voltage VDD) is turned on.Then, the data output line DL is set to the substrate potential from thepower supply voltage VDD. On the other hand, when the node SAT is at thepower supply voltage VDD, the output of the inverter 812 is set to thesubstrate potential VDD. Then, the nMOS transistor N205 is turned off,so that the data output line DL is held at the power supply voltage VDD.

When a write operation is performed, the write control signal /WE is setto the low level (or the substrate potential GND). Then, in the bit linepair selection circuit 802, values of the write data signal lines WDTand WDN are output to the bit line pair BLT and BLN selected by the bitline pair selection signal /YS that is in an active state. That is, whenthe bit line pair selection signal /YS is at a low level and the writecontrol signal /WE is at a low level, an output of the NOR circuit 811becomes the high level (or the power supply voltage VDD). The nMOStransistors N101 and N102 that receive the output of the NOR circuit 811are both turned on. Then, signal levels of a pair of the complementarywrite data signal lines WDT and WDN are transferred to the bit line pairBLT and BLN, respectively.

When the read operation or the write operation is completed, thepre-charge control signal PC is set to the low level. The pMOStransistors P101 to P103 are then turned on, and the bit line pair BLTand BLN is charged to the power supply voltage VDD.

Non-patent Document 1:

“A 2-GHz cycle, 430-ps access time 34-kb L1 directory SRAM in 1.5 V,0.18-um CMOS bulk technology”, R. V. Joshi, 2000 Symposia on VLSIcircuit, pp. 222-225

DISCLOSURE OF THE INVENTION

Problems to be Solved by the Invention

By the way, when the finer geometries are achieved and the number ofmemory cells per bit line is also reduced using a conventional sensingcircuit shown in Non-patent document 1, a problem arises that the delaytime cannot effectively be reduced.

This problem occurs because due to a decrease in the number of thememory cells per bit line, a proportion of the capacitance of thesensing circuit to the entire capacitance of the bit lines hasincreased. This occurs because in the conventional sensing circuit of asemiconductor storage device, in order to reduce the potentialdifference between the bit line pair ΔV_(b1) as much as possible, thesize of a transistor constituting the latch of the sense amplifier isset to be several tens of times that of a memory cell transistor, sothat the capacitance of the bit lines for which the number of the memorycells has been reduced becomes substantially the same as the capacitanceof the sense amplifier.

Further, existences of a diffusion capacitance C_(ys) of a pn-junctionin the bit line pair selection circuit 802 and an on-resistance R of thetransistors (such as the transistors N101, N102, P104, and P105) in thebit line pair selection circuit 802 also become a factor for preventinga high-speed operation.

Assuming that a memory cell diffusion capacitance and a bit line wiringcapacitance are C_(b1), the diffusion capacitance of the bit line pairselection circuit 802 is C_(ys), the capacitance of the sense amplifier803 is C_(sa), and that the on-resistance of the transistors (N101,N102, P104, and P105) of the bit line pair selection circuit 802 is R,the bit line delay time t_(b1) in the above expression (2) is given bythe following expression (3).t _(b1) =C _(b1a)·Δ_(b1) /I _(ce11) +R·C _(b1)·(C _(ys) +C_(sa))/C_(b1a)  (3)where C_(b1a)=C_(b1)+C_(ys)+C_(sa)

When the sizes of the transistors in the bit line pair selection circuit802 are increased to reduce the on resistance R of the transistors, thediffusion capacitance C_(ys) will increase. Thus, the value of the firstterm of the above expression (3) will increase.

Further, when the sizes of the transistors in the bit line pairselection circuit 802 are reduced to reduce the diffusion capacitanceC_(ys), the value of the on-resistance R of the transistors willincrease. Thus, the value of the second term of the above expression (3)will increase.

As shown in the above-mentioned results of study, existence of the bitline pair selection circuit 802 and inability to reduce the sizes of thetransistors in the sense amplifier 803 place a constraint on reductionof the bit line delay time. Meanwhile, this problem is clarified basedon the above-mentioned results of study by the inventor of the presentinvention.

Accordingly, it is an object of the present invention to provide asemiconductor storage device that uses a novel design system in whichwhile suppressing an increase in a chip area, a bit line delay time isreduced, thereby achieving a higher-speed operation of the device.

Means to Solve the Problem

The above and other objects are attained by a semiconductor storagedevice according to a first aspect of the present invention, whicheliminate a conventional bit line pair selection circuit and reduce abit line delay, comprises:

a memory cell array including a plurality of memory cells respectivelydisposed at intersections between a plurality of bit line pairs and aplurality of word lines disposed in a direction orthogonal to the bitline pairs;

a plurality of per-bit sensing circuits respectively connected to eachof the bit line pairs;

each of the per-bit sensing circuits including:

a first circuit connected to a corresponding one of the bit line pairs,for setting voltages at the corresponding one of the bit line pairs to afirst level when a bit line pair selection signal received is inactive;

a second circuit connected to the corresponding one of the bit linepairs and setting the corresponding one of the bit line pairs tomutually complementary levels according to a signal read onto thecorresponding one of the bit line pairs from a selected memory cell whenthe bit line pair selection signal is made active and an input sensingcircuit activation signal is also active; and

a third circuit connected to the corresponding one of the bit linepairs, for receiving a write data signal, and setting one bit line ofthe corresponding one of the bit line pairs set in common to the firstlevel to a second level complementary with the first level, based on thewrite data signal, when the bit line pair selection signal is active,thereby setting complementary write data on the corresponding one of thebit line pairs; and

a data output circuit for receiving respective one bit lines of the bitline pairs from the per-bit sensing circuits, and outputting data readto a selected bit line pair. In the present invention, the data outputcircuit may include:

a fourth circuit for outputting a first logic value when all of the bitlines received are at the first level and outputting a second logicvalue when at least one of the bit lines received is at the secondlevel; and

a fifth circuit for receiving an output signal of the fourth circuit andoutputting read data to a data output line based on a value of theoutput signal.

Each of the per-bit sensing circuits in a semiconductor storage deviceaccording to the present invention includes:

a pre-charge circuit connected to a corresponding one of the bit linepairs, for setting the corresponding one of the bit line pairs to afirst supply potential;

a first latch circuit connected to the corresponding one of the bit linepairs, for setting the other one bit line of the corresponding one ofthe bit line pairs to the first supply potential when one bit line ofthe corresponding one of the bit line pairs is set to a second powersupply potential;

a second latch circuit connected to the corresponding one of the bitline pairs, for assisting setting of the one bit line of thecorresponding one of the bit line pairs to the second power supplypotential when the one bit line of the corresponding one of the bit linepairs is set to the second power supply potential; and

a data write circuit connected to the corresponding one of the bit linepairs, for receiving a write data signal and setting the one bit line ofthe corresponding one of the bit line pairs to the second power supplypotential according to value of the write data signal. Then, control ofactivation/deactivation of the pre-charge circuit, the data writecircuit, and the second latch circuit may be performed according to abit line pair selection signal received.

In the semiconductor storage device according to the present invention,the logic circuit of the data output circuit may include a plurality offifth MOS transistors of a first conductivity type with gates thereofrespectively connected to each of one bit lines of the bit line pairs;

sources of the fifth MOS transistors of the first conductivity type maybe connected in common to the first power supply, and drains of thefifth MOS transistors of the first conductivity type may be connected toone node;

an MOS transistor of a second conductivity type for receiving theinverted signal of the sensing circuit activation signal at a gatethereof and an MOS transistor of the second conductivity type with agate thereof connected to the data output line may be connected inparallel between the one node and the second power supply; and

the one node may be connected to the output transistor at a gatethereof, the output transistor having a source thereof grounded and adrain thereof connected to the data output line. In the presentinvention, the data output circuit may be configured to input each ofthe one bit lines and each of the other bit lines of the bit line pairsof each of the per-bit sensing circuits and differentially output dataread to a selected bit line pair.

In the semiconductor storage device according to the present invention,the data output circuit may include:

an auxiliary circuit that receives the sensing circuit activationsignal, for setting the inverted signal of the sensing circuitactivation signal to the second power supply potential when the sensingcircuit activation signal is at the first supply potential.

In the semiconductor storage device according to the present invention,the memory cell array and the data output unit connected in common tothe per-bit sensing circuits may constitute a basic block;

a plurality of first signal line groups may be spaced apart to oneanother, each of the first signal line groups being constituted from theword lines extended in parallel in one direction, the bit line pairselection signals extended in parallel in the one direction, and thesensing circuit activation signal and the inverted signal of the sensingcircuit activation signal;

a plurality of second signal line groups may be spaced apart to oneanother, each of the second signal line groups being constituted fromthe data output line extended in a direction orthogonal to the onedirection and the complementary lines for the write data signals; and

the semiconductor storage device may include a basic bock arrayincluding the basic blocks provided at intersections between the firstand second signal line groups in an array form.

Meritorious Effect of the Invention

According to the present invention, the sensing circuit of a novelconfiguration that does not use the bit line pair selection circuit usedin a conventional semiconductor storage device is provided. With thisarrangement, a delay caused by a diffusion capacitance and an onresistance in the bit line pair selection circuit is eliminated, so thata bit line delay time can be reduced.

According to the present invention, the number of control signals andtransistors can be simultaneously reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration of a first embodiment of thepresent invention;

FIG. 2 is a diagram showing an example of a configuration of a per-bitsensing circuit in a sensing circuit according to the first embodimentof the present invention;

FIG. 3 is a diagram showing an example of a configuration of a dataoutput circuit in the sensing circuit according to the first embodimentof the present invention;

FIG. 4 is a timing chart for explaining an example of a read operationby the sensing circuit in the first embodiment of the present invention;

FIG. 5 is a timing chart for explaining an example of a write operationby the sensing circuit in the first embodiment of the present invention;

FIG. 6 is a block diagram showing a configuration of a semiconductorstorage device including SRAM basic blocks in the first embodiment ofthe present invention;

FIG. 7 is a diagram showing an example of a configuration of a per-bitsensing circuit according to a second embodiment of the presentinvention;

FIG. 8 is diagrams showing configurations of a conventionalsemiconductor storage device, a bit line pair selection circuit, and asensing circuit, respectively;

FIG. 9A shows a conventional configuration, while FIG. 9B shows aconfiguration of the present invention;

FIG. 10 is a diagram showing a configuration of a per-bit sensingcircuit in a sensing circuit according to a third embodiment of thepresent invention;

FIG. 11 is a diagram showing a configuration of a per-bit sensingcircuit in a sensing circuit according to a fourth embodiment of thepresent invention;

FIG. 12 is a diagram showing a configuration example of a data outputunit in a sensing circuit according to a fifth embodiment of the presentinvention;

FIG. 13 is a diagram showing a configuration example of a data outputunit in a sensing circuit according to a sixth embodiment of the presentinvention; and

FIG. 14 is a diagram showing a configuration example of a data outputunit in a sensing circuit according to a seventh embodiment of thepresent invention.

EXPLANATION OF NUMERALS 101 sensing circuit 102 memory cell array 103,203, 303 per-bit sensing circuit 104, 204, 304, 404 data output unit 105SRAM basic block 106 SRAM basic block 107 data 108 data input/outputunit 109 control unit 110 semiconductor storage device 801 memory cellarray 802 bit line pair selection circuit 803 sense amplifier 811 NORcircuit 812, 813 inverter IV10 inverter N1-N6, N7-N10, N61, N62, nMOStransistor N101-N102, N201-N205 P1-P5, P101-P105, P201-P205 pMOStransistor WL word line YS bit line pair selection signal SE sensingcircuit activation signal /SE inverted signal of sensing circuitactivation signal BLT and BLN bit line pair VDD supply voltage GNDsubstrate voltage /BLT node (output of multi-input NAND gate) DL dataoutput line WDT and WDN write data signal line pair

PREFERRED EMBODIMENTS OF THE INVENTION

A best mode for carrying out the present invention will be described.Referring to FIG. 1, an embodiment mode of the present inventionincludes a memory cell array (102) having a plurality of bit line pairs(BLT and BLN), a plurality of word lines (WL), and a plurality of memorycells disposed at intersections between the bit line pairs and the wordlines, respectively, a plurality of sensing circuits (103) (referred toas “per-bit sensing circuits” because the circuits are the sensingcircuits provided for each bit line pair) connected to the bit linepairs, respectively, and one data output unit (104) provided for theper-bit sensing circuits (103). The data output unit (104) receives onebit line of the bit line pair from each of the per-bit sensing circuits(103), and outputs data read to a selected bit line pair to a dataoutput line (DL). The memory array (102), the per-bit sensing circuits(103), and data output unit (104) constitute a basic block.

In the embodiment mode of the present invention, referring to FIG. 2,the per-bit sensing circuit (103) includes a pre-charge circuit, acircuit for performing amplification, and a data write circuit. Thepre-charge circuit is connected to a bit line pair (BLT and BLN), andsets voltages at the bit line pair (BLT and BLN) to a first level (suchas a supply voltage VDD) when a bit line pair selection signal received(YS) is inactive. The circuit for performing amplification is connectedto the bit line pair (BLT and BLN). When the bit line pair selectionsignal (YS) is made active and when an input sensing circuit activationsignal (SE) is active, the circuit for performing amplification sets thebit line pair (BLT and BLN) to mutually complementary levels (the powersupply voltage VDD and a ground potential GND) according to a signalread onto the bit line pair (BLT and BLN) from a selected memory cell.The data write circuit is connected to the bit line pair (BLT and BLN)and receives a write data signal pair (WDT and WDN). When the bit linepair selection signal (YS) is active, the data write circuit sets one ofthe bit line pair (BLT and BLN) pre-charged to the first level to asecond level (such as the ground potential GND) that is complementarywith the first level, based on the write data signals, thereby settingcomplementary write data on the bit line pair (BLT and BLN).

In the embodiment mode of the present invention, the data output circuitincludes a logic circuit and an output transistor. When all of the bitlines input from the per-bit sensing circuits are at the first level,the data output circuit outputs a first logic value. When at least oneof the bit lines is at the second level, the data output circuit outputsa second logic value. The output transistor inputs an output signal ofthe logic circuit, and outputs read data to the data output line (DL)based on the value of the output signal.

When a more detailed description is given at a transistor level,referring to FIG. 2, the per-bit sensing circuit (103) in the embodimentmode of the present invention includes:

(A1) the pre-charge circuit constituted from first and second MOStransistors of a first conductivity type (P3 and P4) with sourcesthereof connected in common to a first power supply (VDD) and drainsthereof connected to the pair of the bit lines, respectively, and gatesthereof connected to the bit line pair selection signal (YS);

(A2) a first latch circuit constituted from third and fourth MOStransistors of the first conductivity type (P1 and P2) with sourcesthereof connected in common to the first power supply, drains thereofconnected to the first and second bit lines (BLT and BLN) constitutingthe bit line pair, respectively, and gates thereof cross-connected tothe second and first bit lines (BLN and BLT), respectively;

(A3) a second latch circuit including first and second MOS transistors(N1, N2) of a second conductivity type with drains thereof connected tothe first and second bit lines (BLT and BLN) constituting the bit linepair, respectively, gates thereof cross-connected to the second andfirst bit lines (BLN and BLT), respectively, and sources thereofconnected in common, and a third MOS transistor (N3) of the secondconductivity type connected between a common connecting node between thesources of the first and second MOS transistors and an inverted signal(/SE) of the sensing circuit activation signal, with a gate thereofconnected to the bit line pair selection signal (YS), for being subjectto on/off control; and

(A4) the data write circuit including fourth and fifth MOS transistors(N4 and N5) of the second conductivity type with drains thereofconnected to the first and second bit lines (BLT and BLN) constitutingthe bit line pair, gates thereof connected to a pair of lines for thecomplementary write data signals (WDT and WDN), respectively, andsources thereof connected in common, and a sixth MOS transistor (N6) ofthe second conductivity type connected between a common connecting nodebetween the sources of the fourth and fifth MOS transistors and thesecond power supply potential (GND), with a gate thereof connected tothe bit line pair selection signal (YS), for being subject to on/offcontrol.

In the present embodiment mode, the logic circuit of the data outputcircuit (104) is constituted from a multi-input negative AND (NAND) gateof a dynamic type. That is, when all the bit lines from the per-bitsensing circuits are at the first supply potential (VDD), the logicallevel of an output node (/BLT) is made low. The output transistor (N9)with a source thereof grounded, a drain thereof connected to the dataoutput line (DL), and a gate thereof connected to an output node of theNAND gate is thus turned off. On the other hand, when at least one ofthe bit lines (a selected bit line) is at the second power supplypotential, the output node (/BLT) of the NAND gate becomes high. Theoutput transistor (N9) is thereby turned on, and the data output line DLis discharged to the second power supply potential (GND).

In the present embodiment mode, the data output circuit (104) includesan auxiliary circuit (N10) for receiving the sensing circuit activationsignal SE and setting the inverted signal of the sensing circuitactivation signal (/SE) to the second power supply potential (GND) whenthe sensing circuit activation signal is at the first supply potential(VDD).

In the present embodiment mode, the logic circuit of the data outputcircuit (104) includes a plurality of fifth MOS transistors (P5) of thefirst conductivity type with gates thereof connected to one bit lines ofthe pairs of the bit lines. Sources of the fifth MOS transistors of thefirst conductivity type are connected in common to the first powersupply VDD, and drains of the fifth MOS transistors are connected incommon to the one node (/BLT). Between the one node and the second powersupply GND, a seventh MOS transistor (N7) of the second conductivitytype which inputs the inverted signal of the sensing circuit activationsignal at a gate thereof and an eighth MOS transistor (N8) of the secondconductivity type with a gate thereof connected to the data output lineare connected in parallel with each other.

In the present embodiment mode, the data write circuit for dischargingone bit line of the selected pair of the bit lines to the potential of asubstrate (GND: ground potential) at a time of a write operation iscontrolled by the bit line pair selection signal (YS), sensing circuitactivation signal /SE, and pair of the write data signal lines WDT andWDN.

The second latch circuit for accelerating a discharging operation on onebit line of the selected pair of the bit lines to be discharged due to amemory cell at a time of a read operation is controlled by the bit linepair selection signal (YS) and the sensing circuit activation signal(/SE). The data output circuit (104) is controlled by the sensingcircuit activation signal /SE.

This embodiment mode includes a basic block array. The basic block arrayis constituted by including a first signal line group, a second signalline group, and a basic block array. The first signal line group isconstituted from the word lines (WL) extended in parallel in onedirection, the bit line pair selection signals (YS) extended in parallelin the one direction, and the sensing circuit activation signals (SE)and the inverted signals thereof (/SE). The word lines, the bit linepair selection signals, and the sensing circuit activation signals andthe inverted signals of the sensing circuit activation signals arespaced apart to one another. The second signal line group is constitutedfrom the data output lines (DL) and the pairs of the complementary writedata signal lines (WDT and WDN) which are extended in a directionorthogonal to the one direction, and spaced to one another. Atintersections between the first and second signal line groups, the basicblocks (105) are included in an array form.

Embodiments

Embodiments of the present invention will be described below in detailwith reference to drawings. FIG. 1 is a diagram showing a basicconfiguration of a static random access memory (SRAM) according to afirst embodiment of the present invention. The basic configuration ofthe SRAM is configured by including a sensing circuit 101 for performingan n-to-one bit line pair selection (selection of one bit line pair fromn bit line pairs) and the memory cell array 102 having a plurality (m)of word lines WL and n plural (n pairs of) bit line pairs. A memory cellnot shown in the memory cell array 102 includes a flip-flop constitutedby cross connecting inputs and outputs of two inverters and two passtransistors (also referred to as “access transistors”) connected betweena connecting node of the inputs and the outputs of the two inverters andrespective bit lines of a bit line pair. Gates of the two passtransistors are connected in common to a word line.

The sensing circuit 101 includes n per-bit sensing circuits 103 eachconnected to a bit line pair BLT and BLN and the data output unit 104connected to the bit line BLT from each of the per-bit sensing circuits103.

The per-bit sensing circuits 103 are connected to the bit line pairselection signal YS. Activation of the per-bit sensing circuits 103 iscontrolled by the sense amplifier activation signal /SE. The per-bitsensing circuits are connected to the pair of complementary write datasignal lines WDT and WDN. The data output unit 104 is connected to thedata output line DL sensing circuit activation signal SE, and invertedsignal SE thereof.

FIG. 2 is a diagram showing an example of a circuit configuration of theper-bit sensing circuit 103 in FIG. 1. Referring to FIG. 2, the per-bitsensing circuit 103 includes the pMOS transistors P3 and P4, pMOStransistors P1 and P2, nMOS transistors N1 and N2, transistor N3, nMOStransistors N4 and N5, and nMOS transistor N6. The pMOS transistors P3and P4 have sources connected in common to the power supply VDD, havedrains connected to the bit lines BLT and BLN, respectively, and havegates connected in common to the bit line pair selection signal YS. ThepMOS transistors P1 and P2 have sources connected in common to the powersupply VDD, have drains connected to the bit line pair BLT and BLN,respectively, and have gates are cross-connected to the bit lines BLNand BLT, respectively. The nMOS transistors N1 and N2 have drainsconnected to the bit line pair BLT and BLN, respectively, and have gatescross-connected to the bit lines BLN and BLT, respectively. Thetransistor N3 has a drain connected to a common connecting point betweenthe sources of the nMOS transistors N1 and N2, has a source connected tothe inverted signal /SE of the sensing circuit activation signal, andhas a gate connected to the bit line pair selection signal YS. The nMOStransistors N4 and N5 have drains connected to the bit line pair BLT andBLN, respectively, and have gates connected to the pair of the writedata signal lines WDT and WDN. The nMOS transistor N6 has a drainconnected to the common connecting point between the sources of the nMOStransistors N4 and N5, has a source grounded (or connected to thesubstrate potential GND), and has a gate connected to the bit line pairselection signal YS.

When the bit line pair selection signal YS is inactive (at a low level),or when the bit line pair BLT and BLN is not selected, the pMOStransistors P3 and P4 charge the bit line pair BLT and BLN to the powersupply voltage VDD.

When one of the selected bit line pair BLT and BLN is discharged to thesubstrate potential GND due to a memory cell, the pMOS transistors P1and P2 sets the other of the bit line pair BLT and BLN to the powersupply voltage VDD.

When a read operation is performed, the nMOS transistors N1 and N2accelerate a discharging operation on one bit line of the selected bitline pair BLT and BLN to be discharged due to the selected memory cell.When one bit line BLT of the selected bit line pair BLT and BLN isassumed to be discharged, the nMOS transistor N1 with the gate thereofconnected to the other bit line BLN of the selected bit line pair BLTand BLN is turned on. The one bit line BLT is electrically connected tothe sensing circuit activation signal /SE at the substrate potential GNDand set to the substrate potential GND through the nMOS transistors N1and N3 in an on state.

When a write operation is performed, the nMOS transistors N4 and N5discharge one bit line of the selected bit line pair BLT and BLN to thesubstrate potential GND. When one write data signal line WDT of thewrite data signal line pair is at the power supply voltage VDD and theother write data signal line WDN is at the substrate potential GND, thenMOS transistor N4 is turned on, and the nMOS transistor N5 is turnedoff. Then, the bit line BLT is set to the substrate potential (GND)through the nMOS transistors N4 and N6.

FIG. 3 is a diagram showing an example of a circuit configuration of thedata output circuit 104 for performing the n-to-one bit line pairselection at a time of the read operation. Referring to FIG. 3, the dataoutput circuit 104 includes the pMOS transistor P5, an nMOS transistorN9, the nMOS transistor N7, the nMOS transistor N8, and the nMOStransistor N11. The pMOS transistor P5 has a source connected to thepower supply VDD, has a gate connected to the bit line BLT, and has adrain connected to the node /BLT. The nMOS transistor N9 has a gateconnected to the node /BLT, has a source grounded and has a drainconnected to the data output line DL. The nMOS transistor N9 constitutesan output circuit (inverted amplifier circuit). The inverted signal /SEof the sensing circuit activation signal SE is supplied to the gate ofthe nMOS transistor N7. The nMOS transistor N7 has a drain connected tothe node /BLT, and has a source connected to the substrate potentialGND. The nMOS transistor N8, which is connected in parallel with thenMOS transistor N7 between the node /BLT and the substrate potentialGND, has a gate connected to the data output line DL. The nMOStransistor N10, which is connected between the inverted signal /SE ofthe sensing circuit activation circuit SE and the substrate potentialGND, has a gate connected to the bit line pair selection signal SE. Thedrains of n pieces of pMOS transistors P5 provided corresponding to nbit lines BLT from the n pieces of per-bit sensing circuits 103 areconnected in common to the node /BLT. The sources of the n pieces ofpMOS transistors P5 are connected in common to the power supply VDD.Incidentally, in FIG. 3, one pMOS transistor P5 is shown for simplicityof the description, and pMOS transistors P5 connected in parallelbetween the power supply VDD and the node /BLT is indicated as “xn”.

The nMOS transistor N10 is turned on when the sensing circuit activationsignal SE is activated (to the power supply voltage VDD), and assistsdischarging of the inverted signal /SE of the sensing circuit activationsignal. The nMOS transistor N10 sets the inverted signal /SE of thesensing circuit activation signal to the substrate potential GND.

The pMOS transistor P5 outputs inverted data of the potential of one bitline BLT of a selected bit line pair to the node /BLT. When the bit lineBLT is at a low level, the pMOS transistor P5 is turned on, and drivesthe node /BLT to the power supply voltage VDD. When the bit line BLT isat a high level, the pMOS transistor P5 is turned off, and the node /BLTis set to the substrate potential GND. When all of the n bit lines BLTare at a high level (or at the power supply voltage VDD), the node /BLTis set to the substrate potential GND, the nMOS transistor N9 is turnedoff, and the data output line DL is kept at the power supply voltageVDD. When the bit line BLT of the selected bit line pair is at a lowlevel, the node /BLT is set to the power supply voltage VDD, the nMOStransistor N9 is turned on, and the data output line DL is set to thesubstrate potential GND.

The n pMOS transistors P5, nMOS transistors N7 and N8 constitute ann-input NAND gate of a dynamic type. A logic gate of the dynamic typerefers to a circuit for implementing a logical function by storingelectric charge in a node that is not connected to a power supply.

The nMOS transistor N7 is turned on when the inverted signal /SE of thesensing circuit activation signal is at a high level (or at the powersupply voltage VDD), and discharges the node /BLT to the subtratepotential GND.

The nMOS transistor N8 prevents the node /BLT from becoming a floatingstate when the potential of a bit line selected at a time of activationof the sensing circuit is the power supply voltage VDD. When theselected bit line BLT is at the power supply voltage VDD (with the dataoutput line DL being at the power supply voltage VDD), the nMOStransistor N8 is turned on to set the node /BLT to the substratepotential GND, and the transistor N9 is turned off.

FIG. 4 is a timing chart explaining a read operation from a basic block105 of the SRAM according to the present embodiment. FIG. 4 showsvoltage waveforms of a clock signal, the word line WL, the bit line pairselection signal YS, the sensing circuit activation signal SE and thesignal /SE, the bit line pair BLT and BLN, the pair of the complementarywrite data signal lines WDT and WDN, node /BLT, and data output line DL.The present embodiment shows the SRAM of a clock synchronous type. Theclock in FIG. 4 corresponds to a clock signal in FIG. 6 which will bedescribed later, and is an internal clock signal generated based on anexternal clock signal for synchronization supplied from an outside of asemiconductor storage device. A read operation in the present embodimentwill be described with reference to FIGS. 2 through 4.

At a time of the read operation, one word line WL selected from the mword lines is activated in synchronization with a rising edge of theclock signal at a time t1, and the word line WL is raised from thesubstrate potential GND to the power supply voltage VDD. At the sametime, the signal YS for selecting one bit line pair from among the n bitline pairs is activated to (the power supply voltage VDD). In theper-bit sensing circuit 103 shown in FIG. 2, the pMOS transistors P3 andP4 are turned off, and the nMOS transistor N6 is turned on. By theactivation of the selected word line WL and turning off of the pMOStransistors P3 and P4, one bit line of the bit line pair BLT and BLNwhich has been pre-charged to the power supply voltage VDD is dischargedbased on the value of cell data.

After a predetermined time from the activation of the word line WL, thesensing circuit activation signal SE is activated, (thereby rising tothe power supply voltage VDD). The inverted signal /SE of the sensingcircuit activation signal falls to the substrate potential GND from thepower supply voltage VDD.

This accelerates a discharging operation of one bit line out of the bitline pair BLT and BLN through the MOS transistor N3 that has been turnedon in advance and one of the transistors N1 and N2, which has a gateconnected to the bit line at the power supply voltage, in the per-bitsensing circuit 103 in FIG. 2.

Then when the bit line to be discharged is the bit line BLT, the pMOStransistor P5 is turned on in the data output unit 104, so that the node/BLT is raised from the substrate potential GND to the power supplyvoltage VDD. This turns on the nMOS transistor N9, so that the dataoutput line DL lowered from the power supply voltage VDD to thesubstrate potential GND. The read operation is executed by stepsdescribed above.

Next, when the word line WL and the bit line pair selection signal YSare lowered from the power supply voltage VDD to the substrate potentialGND in synchronization with a fall transition of the clock signal at atime t2 in FIG. 4, the pMOS transistors P3 and P4 in the per-bit sensingcircuit 103 in FIG. 2 are turned on. The one bit line of the bit linepair BLT and BLN that has been discharged is raised from the substratepotential GND to the power supply voltage VDD. When the sensing circuitactivation signal SE is lowered from the power supply voltage VDD to thesubstrate potential GND after a predetermined time, the inverted signal/SE thereof is raised from the substrate potential GND to the powersupply voltage VDD. Then, the nMOS transistor N7 is turned on, the node/BLT is initialized to the substrate potential GND, and the transistorN9 is turned off. Incidentally, a period from the time t1 to a time t3form one read cycle.

On the other hand, as shown in the read cycle starting from the time t3in FIG. 4, when the sensing circuit activation signal SE is activated(when the sensing circuit activation signal SE is raised to the powersupply voltage VDD), and when the discharged bit line of the bit linepair is the bit line BLN (when the bit line BLT is at the power supplyvoltage), the pMOS transistor P5 in the data output unit 104 in FIG. 3is turned off, and the transistor N7 is turned on. Thus, the node /BLTis kept at the substrate potential GND. This turns off the transistorN9, and the data output line DL is held at the power supply voltage VDD.At this point, the nMOS transistor N8 is also turned on, so that thenode /BLT is held at the substrate potential GND.

FIG. 5 is a timing chart showing a write operation in the presentembodiment. Referring to FIG. 5, at a time of the write operation, anoperation of activating one of the write data signal lines WDT and WDNaccording to write data, in synchronization with the clock signal, isadded to the read operation described with reference to FIG. 4.

Referring to FIG. 5, in a period from activation of the word line signalWL and the bit line pair selection signal YS in synchronization with arise transition of the clock signal at a time t1 to activation of thesensing circuit activation signal SE, one of the pair of thecomplementary write data signal lines WDT and WDN is activated accordingto write data. This turns on the transistor N6 in the per-bit sensingcircuit 103, one of the transistors N4 and N5 with the gate thereofconnected to the write data signal line at a high level is turned on,and one of the bit line pair BLT and BLN connected to the transistor inthe on state is discharged to the substrate potential GND.

When the one of the bit line pair BLT and BLN is discharged to a certainpotential or less, the write data is supplied to the node of a selectedmemory cell (the input/output node of the flip-flop). A write operationis executed by steps described above.

Then, when the word line WL and the bit line pair selection signal YSare lowered from the power supply voltage VDD to the substrate potentialGND in synchronization with a fall of the clock signal at a time t2 inFIG. 5, the pMOS transistors P3 and P4 in the per-bit sensing circuit103 in FIG. 2 are turned on. The one bit line of the bit line pair BLTand BLN that has been discharged is raised from the substrate potentialGND to the power supply voltage VDD (with the other remaining at thepower supply voltage VDD), so that a pre-charging operation isperformed. When the sensing circuit activation signal SE is lowered fromthe power supply voltage VDD to the substrate potential GND after apredetermined time, the inverted signal /SE thereof is raised from thesubstrate potential GND to the power supply voltage VDD. Meanwhile,initialization of the respective signals in the write operation isperformed in the same manner as in the read operation.

FIG. 6 is a diagram showing a configuration of a semiconductor storagedevice 110 constituted by arranging a plurality of SRAM basic blocks105, one of which was described with reference to FIGS. 1 through 5. Thesemiconductor storage device 110 includes M first signal line groups, Nsecond signal line groups, and an SRAM basic block array 106. Each ofthe M first signal line groups is constituted from the plurality (m) ofthe word lines WL (1 to m) extended in parallel in a horizontaldirection of the drawing, the plurality (n) of the bit line pairselection signals YS (1 to n) extended in parallel in the horizontaldirection, and the sensing circuit activation signal SE and the invertedsignal /SE thereof extended in parallel in the horizontal direction. TheM first signal line groups are separated to one another. Each of the Nsecond signal line groups is constituted from the data output line DLand the pair of the complementary write data signal lines WDT and WDN,extended in a vertical direction of the drawing. The N second signalline groups are separated to one another. The SRAM block array 106 isconstituted by including M×N SRAM basic blocks 105 provided atintersections between the first signal line groups and the second signalline groups. The semiconductor storage device 110 further includes adecoder 107, a data input/output unit 108, and a control unit 109. Thedecoder 107 is connected to the word lines WL, bit line pair selectionsignals YS, sensing circuit activation signals SE, inverted signals /SEof the sensing circuit activation signals, and controls an operation ofthe SRAM basic block array 106. The data input/output unit 108 isconnected to the pairs of the write data signal lines WDT and WDN, andthe data output signal lines DL. The data input/output unit 108 performscontrol over a write operation of the SRAM basic block array 106 andperforms data input and output. The control unit 109 inputs an addresssignal, the clock signal and control signals and controls the decoder107 and the data input/output unit 108. The decoder 107 includes a rowdecoder for decoding a row address and activating a selected word lineand a column decoder for decoding a column address and activating thebit line pair selection signal YS associated with a selected bit linepair. The control unit 109 performs control of a read/write operationover the decoder 107 and the data input/output circuit 108 based on thecontrol signal, generates a strobe signal for activating the selectedword line in synchronization with the clock signal or the like, andcontrols timings of activating the bit line pair selection signal YS andthe sensing circuit activation signal SE. Incidentally, in the SRAM ofthe clock synchronization type, latching of the address signal, writedata signal, and control signals which are supplied from the outside,and output of a read data signal to the outside are performed insynchronization with the clock signal.

FIG. 7 is a diagram showing an example of a circuit configuration of aper-bit sensing circuit 203 according to a second embodiment of thepresent invention. Referring to FIG. 7, in the per-bit sensing circuit203 in the second embodiment of the present invention, the nMOStransistor N6 in the per-bit sensing circuit 103 in the above describedembodiment shown in FIG. 2, is configured to be separated into twotransistors N61 and N62. That is, the per-bit sensing circuit 203includes an nMOS transistor N4, the nMOS transistor N61, an nMOStransistor N5, and the nMOS transistor N62. A drain of the nMOStransistor N4 is connected to the bit line BLT and a gate of the nMOStransistor N4 is connected to one write data signal line WDT of thewrite data signal line pair. A source of the nMOS transistor N61 isconnected to the substrate potential GND, a gate of the nMOS transistorN61 is connected to the bit line pair selection signal YS. A drain ofthe nMOS transistor N61 is connected to a source of the nMOS transistorN4. A drain of the nMOS transistor N5 is connected to the bit line BLN,and to a gate of the nMOS transistor N5, the write data signal line WDN,which is the other one of the write data signal line pair, is connected.A source of the nMOS transistor N62 is connected to the substratepotential GND. A gate of the nMOS transistor N62 is connected to the bitline pair selection signal YS, and a drain of the nMOS transistor N62 isconnected to a source of the nMOS transistor N5.

The order of the nMOS transistor N4 and the nMOS transistor N61connected in series between the bit line BLT and the substrate potentialGND may be of course exchanged, and the order of the nMOS transistor N5and the nMOS transistor 62 connected in series between the bit line BLNand the substrate potential GND may be of course exchanged. That is, thecircuit may be configured to include the nMOS transistor N61 with thedrain thereof connected to the bit line BLT and the gate thereofconnected to the bit line pair selection signal Y, the nMOS transistorN4 with a source thereof connected to the substrate potential GND, thegate thereof connected to the one write data signal line WDT of thewrite data signal line pair, and the drain thereof connected to thesource of the nMOS transistor N61, the nMOS transistor N62 with thedrain thereof connected to the bit line BLN and the gate thereofconnected to the bit line pair selection signal YS, and the nMOStransistor N5 with a source thereof connected to the substrate potentialGND, the gate thereof connected to the other write data signal line WDNof the write data signal line pair, and the drain thereof connected tothe source of the nMOS transistor N62.

An operation and effect of the above-mentioned embodiment will bedescribed.

In the present embodiment, by configuring the sensing circuit withoutusing a bit line pair selection circuit employed in a conventionalsemiconductor storage device, a bit line delay time t_(b1) can bereduced.

In a conventional sensing circuit, for example, in case wherein acapacitance C_(bla) is set to 40 fF, a capacitance C_(ys) is set to 20fF, a capacitance C_(sa) is set to 20 fF, a ratio ΔV_(b1)/I_(cell) isset to 1 KΩ, and a resistance R is set to 2 kΩ, the bit line delayt_(b1) becomes 120 ps according to the above expression (3).

In the above embodiment, by eliminating a bit line pair selectioncircuit 802 used in the conventional semiconductor storage device, thediffusion capacitance C_(ys) and the on resistance R can be eliminated.Thus, a higher-speed operation in which the bit line delay t_(b1) isreduced to 60 ps is possible, according to the above expression (3).That is, the bit line delay can be substantially reduced to as little ashalf of the delay obtained with a conventional system.

Another operation and effect of the above embodiment is that the numberof the control signals and the transistors can be reduced. The reasonfor that is that in the present embodiment, activation of the pre-chargecircuit (P1 and P2) for fixing the bit line pairs that are not selectedat the power supply voltage and the data write circuit (N4 and N5, andN6) for discharging one bit line of a selected bit line pair to thesubstrate potential at a time of a write operation, and a second latchcircuit (N1, N2, and N3) for accelerating the discharging operation ofthe one bit line of the selected bit line pair to be discharged due to amemory cell at the time of the write operation is controlled by the samebit line pair selection signal YS. A CMOS gate for performing a logicaloperation on the control signals such as an NOR circuit 811 in FIG. 8therefore becomes unnecessary. That is, in the present embodiment, thenumber of the transistors in the block per bit line pair becomes 11,which is the same number of the transistors as the conventional circuit.When an eight-to-one selection (selection of one pair from eight bitline pairs) is used in the sensing circuit as a whole, the number of thetransistors can be reduced to 92 from 102 in the conventionalsemiconductor storage device.

While the number of the control signals is seven constituted from theclock signal, PC signal, signal /WE, signal /YS, signal SAE, signal RSE,and signal WDT (WDN) in the conventional semiconductor storage deviceshown in FIG. 8, the number of the control signals in the presentembodiment is reduced to 4 constituted from the clock signal, signal YS,signal WDT(WDN), and signal /SE(SE).

In the above embodiment, a description was given to an example in whichthe present invention has been applied to the high-speed SRAM of theclock synchronization type. The sensing circuits in the embodimentsdescribed above (e.g. configurations in which the bit line selectioncircuit is eliminated, thereby reducing the bit line delay) can be ofcourse applied to a read and write circuit in a bit line system in theSRAM of an asynchoronous type. In the present invention, at a time ofchanging the order between an amplifying operation and a selectingoperation, a conventional sense amplifier circuit 803 is not used simplyas the per-bit sensing circuits 103, and a charging operation on a bitline pair using the bit line pair selection signal YS is performed. Thepresent invention thereby has an effect in which the number of thetransistors in the data output unit 104 can be reduced. This is because,compared with a case where an ordinary selector was used, the chargingoperation on the bit line pair using the bit line pair selection signalYS has enabled the selecting operation just a mere dynamic NAND gate inthe data output unit 104. With this arrangement, the number of 3×ntransistors is reduced in the data output circuit 103 in FIG. 9B.Further, by using the per-bit sensing circuit 103, the three controlsignals of the PC signal and the signals /WE and RSE are reduced.

The conventional sense amplifier in FIG. 8 and a proposed senseamplifier in FIG. 1 will be shown below. In order to speed up the readoperation (or reduction of the bit line delay), the read operation ischanged as follows. Referring to FIG. 8, after the selecting operationhas been performed in the block 802, the amplifying operation isperformed in the block 803. In this case, the time required for theselecting operation is included in the bit line delay. The bit linedelay will be thereby increased, which will become a problem. In aproposed method, the order between these two operations is exchanged,thereby solving the problem. Referring to FIG. 1, after the amplifyingoperation has been performed at the block 103, the selecting operationis performed at the block 104. With this arrangement, a delay caused bythe selecting operation can be excluded from the bit line delay.Referring to FIG. 1, though a time required for a selecting operation inthe block 104 is additionally included in the bit line delay, the timeof the bit line delay is smaller than a delay time caused by theselecting operation with a conventional method.

Next, the principle of the present invention will be described, usingthe conventional sense amplifier shown in FIG. 8 as a comparativeexample for contrast. FIG. 9A shows a configuration of a semiconductorstorage device using the conventional sense amplifier shown in FIG. 8.FIG. 9B shows a configuration of the present invention shown in FIG. 1.As clear from FIGS. 9A and 9B, in the present invention (in FIG. 9B), inorder to speed up the read operation (or reduction of the bit linedelay), the order between the bit line selecting operation and theamplifying operation for the read operation is changed, compared withthe configuration shown in FIG. 9A. That is, in the case of theconfiguration shown in FIG. 9A, after the selecting operation has beenperformed at the bit line pair selection circuit 802, the senseamplifier 803 performs the amplifying operation on data on a bit line.In the case of such a configuration, a time required for the bit lineselecting operation at the bit line pair selection circuit 802 will beincluded in the bit line delay. The bit line delay will be therebyincreased, which will become the problem.

On contrast therewith, the present invention is configured to includethe data output unit 104 for receiving the bit lines from the per-bitsensing circuits 103 and outputting data read onto a selected bit lineto a data output line, as shown in FIG. 9B. The order between the twooperations (of the selecting operation and the amplifying operation)shown in FIG. 9A is exchanged. As shown in FIG. 9B, according to thepresent invention, after the amplifying operation has been performed atthe per-bit sensing circuit 103, the selecting operation is performed atthe data output unit 104. With this arrangement, the delay time causedby the bit line selecting operation can be excluded from the bit linedelay. Incidentally, in the case of the configuration of the presentinvention in FIG. 9B, the time for the selecting operation is added atthe data output unit 104. This time, however, is shorter than the delaytime caused by the bit line selecting operation in the conventionalmethod shown in FIG. 9A.

FIG. 10 is a diagram showing a configuration of a third embodiment ofthe present invention. It is the diagram showing a variation example ofthe per-bit sensing circuit 103 in FIG. 1. Referring to FIG. 10, thisper-bit sensing circuit 303 is configured by separating the nMOStransistor N3 (which has a gate connected to the signal YS and is off/oncontrolled) in the per-bit sensing circuit 103 shown in FIG. 2 into twotransistors of nMOS transistors N31 and N32 (which have gates connectedin common to the signal YS and is off/on controlled). That is, theper-bit sensing circuit 303 is configured to include an nMOS transistorN1 and the nMOS transistor N31 connected in series with each otherbetween the bit line BLT and the signal /SE and an nMOS transistor N2and the nMOS transistor N32 connected in series with each other betweenthe bit line BLN and the signal /SE. Locations of nMOS transistors N1and N31 connected in series may be exchanged. The same holds true forthe nMOS transistors N2 and N32. Configurations other than these are thesame as those in the example shown in FIG. 2. Thus, a description aboutthe operation of the circuit will be omitted.

FIG. 11 is a diagram showing a configuration of a fourth embodiment ofthe present invention, and is the diagram showing a variation example ofthe per-bit sensing circuit 103 in FIG. 1. Referring to FIG. 11, thisper-bit sensing circuit 403 is configured by separating an nMOStransistor N3 (which has a gate connected to the signal YS and is on/offcontrolled) of the per-bit sensing circuit 203 shown in FIG. 7 into twotransistors of nMOS transistors N31 and N32 (which have gates connectedin common to the signal YS and on/off controlled). The per-bit sensingcircuit 403 includes an nMOS transistor N1 and the nMOS transistor N31connected in series with each other between the bit line BLT and thesignal /SE and an nMOS transistor N2 and the nMOS transistor N32connected in series with each other between the bit line BLN and thesignal /SE. Locations of nMOS transistors N1 and N31 connected in seriesmay be exchanged. The same holds true for the nMOS transistors N2 andN32. Configurations other than these are the same as those in theexample shown in FIG. 7.

FIG. 12 is a diagram showing a configuration of a fifth embodiment ofthe present invention, and is the diagram showing a variation example ofthe data output circuit 104 shown in FIG. 3. Referring to FIG. 12, inthis data output circuit 204, a pMOS transistor is added to the nMOStransistor N10 in the data output circuit 104 shown in FIG. 3, therebyconfiguring a CMOD inverter IV10 (including the pMOS transistor whichhas a source connected to the power supply VDD and has a gate connectedto the control signal SE, and the nMOS transistor N10 which has a drainconnected to a drain of the pMOS transistor, has a gate connected to thesignal SE, and has a source connected to the GND with the signal /SEbeing output from a connecting point between the drains of the pMOStransistor and the NMOS transistor). The control signal wiring /SE inFIG. 3 (supplied to the data output unit 104 from the outside) isthereby omitted.

FIG. 13 is a diagram showing a configuration of a sixth embodiment ofthe present invention, and is the diagram showing a still anothervariation example of the data output unit 104 shown in FIG. 3. The dataoutput unit 104 shown in FIG. 3 is configured to output the data signalto the data output line DL in single ended. Referring to FIG. 13, thisdata output unit 304 is configured to differentially output the datasignal. That is, the data output line DL in FIG. 3 is constituted from apair of complementary signal lines, and data output lines DLT and DLN.The pMOS transistor P5 (which has a gate connected to the bit line BLT,has a source connected to the power supply VDD, and has a drainconnected to the node /BLT) in FIG. 3 is separated into pMOS transistorsP51 and P52 in FIG. 13, and arranged. The pMOS transistor P51 has a gateconnected to the bit line BLT, has a source connected to the powersupply VDD, and has a drain connected to the node /BLT. The pMOStransistor P52 has a gate connected to the bit line BLN, has a sourceconnected to the power supply VDD, and has a drain connected to a node/BLN. The nMOS transistor N7 (transistor for resetting) in FIG. 3,connected between the node /BLT and a ground, is separated into nMOStransistors N71 and N72 in the example shown in FIG. 13. The nMOStransistor N71 is connected between the node /BLT and the GND, while thenMOS transistor N72 is connected between the node /BLN and the GND.Gates of the nMOS transistors N71 and N72 are both connected to thesignal /SE. The nMOS transistor N8 in FIG. 3, connected between the node/BLT and the GND, is separated into nMOS transistors N81 and N82 in theexample shown in FIG. 13. The nMOS transistor N81, connected between thenode /BLT and the GND, has a gate connected to the node /BLN. The nMOStransistor N82, connected between the node /BLN and the GND, has a gateconnected to the node /BLT. The nMOS transistor N9 in FIG. 3, connectedbetween the data output line DL and the ground GND is separated intonMOS transistors N91 and N92 in the example shown in FIG. 13. The nMOStransistor N91, connected between the data output line DLT and the GND,has a gate connected to the node /BLT. The nMOS transistor N92,connected between the data output line DLN and the GND, has a gatethereof is connected to the node /BLT.

FIG. 14 is a diagram showing a configuration of a seventh embodiment ofthe present invention, and is the diagram showing a still anothervariation example of the data output unit 104 shown in FIG. 13. Thisdata output unit 404 is obtained by applying the configuration in FIG.12 to the data output unit 104 in FIG. 13. Referring to FIG. 14, in thisdata output unit 404, a PMOS transistor is added to the nMOS transistorN10 in the data output unit 304 in FIG. 13, thereby configuring a CMOSinverter IV10. The control signal /SE is thereby omitted.

The foregoing description was given in connection with the embodimentsdescribed above. The present invention, however, is not limited to onlythe configurations of the embodiments described above, and of courseincludes various variations and modifications that could be made bythose skilled in the art within the scope of inventions of claims.

1. A semiconductor storage device comprising: a memory cell arrayincluding a plurality of memory cells respectively disposed atintersections between a plurality of bit line pairs and a plurality ofword lines disposed in a direction orthogonal to said bit line pairs;and a plurality of per-bit sensing circuits connected to said pluralityof bit line pairs respectively; each of said per-bit sensing circuitsincluding: a first circuit connected to a corresponding one of said bitline pairs, for setting voltages at the corresponding one of said bitline pairs to a first level when a bit line pair selection signalreceived is in an inactive state; a second circuit connected to thecorresponding one of said bit line pairs, for setting the correspondingone of said bit line pairs to mutually complementary levels according toa signal read onto the corresponding one of said bit line pairs from aselected memory cell when the bit line pair selection signal is in anactive state and a sensing circuit activation signal received is also inan active state; and a third circuit connected to the corresponding oneof said bit line pairs, for receiving a write data signal, and settingone bit line of the corresponding one of said bit line pairs, which areset in common to the first level, to a second level complementary withsaid first level, based on the write data signal, when the bit line pairselection signal is in an active state, thereby setting complementarywrite data on the corresponding one of said bit line pair; saidsemiconductor storage device further comprising a data output circuitfor receiving respective one bit lines of said bit line pairs from saidper-bit sensing circuits, and outputting data read onto a selected bitline pair.
 2. The semiconductor storage device according to claim 1,wherein said data output circuit comprises: a fourth circuit foroutputting a first logic value when all of the bit lines received are atthe first level and outputting a second logic value when at least one ofsaid bit lines received is at the second level; and a fifth circuit forreceiving an output signal of said fourth circuit and outputting readdata to a data output line based on a value of the output signal.
 3. Thesemiconductor storage circuit according to claim 1, wherein in said eachof said per-bit sensing circuits, the second circuit comprises: a firstlatch circuit connected between the corresponding one of said bit linepairs, for setting the one bit line of the corresponding one of said bitline pairs to the first level from a power supply corresponding to thefirst level, responsive to the signal read onto the corresponding one ofsaid bit line pairs from the selected memory cell; and a second latchcircuit for connecting the other bit line of the corresponding one ofsaid bit line pairs to a power supply potential corresponding to thesecond level, thereby setting the other bit line of the correspondingone of said bit line pairs to the second level; said second latchcircuit being connected to the power supply potential corresponding tothe second level through a switch which is subject to on/off control bythe bit line pair selection signal.
 4. The semiconductor storage deviceaccording to claim 3, wherein in the second latch circuit, the powersupply potential corresponding to the second level is supplied from aline of an inverted signal of the sensing circuit activation signal. 5.The semiconductor storage device according to claim 1, wherein saidmemory cell array, said per-bit sensing circuits, and said data outputcircuit constitute a basic block; a plurality of first signal linegroups are spaced apart to one another, said first signal line groupsincluding said word lines extended in parallel in one direction, the bitline pair selection signals extended in parallel in the one direction,and the sensing circuit activation signal and the inverted signal of thesensing circuit activation signal; a plurality of second signal linegroups are spaced apart to one another, including the data output lineextended in a direction orthogonal to the one direction and thecomplementary lines for the write data signals; and said semiconductorstorage device comprises a basic bock array including the basic blocksprovided at intersections between the first and second signal linegroups in an array form.
 6. A semiconductor storage circuit comprising:a memory cell array including a plurality of memory cells respectivelydisposed at intersections between a plurality of bit line pairs and aplurality of word lines disposed in a direction orthogonal to said bitline pairs; a plurality of per-bit sensing circuits connected to saidplurality of bit line pairs, respectively ; and a data output circuitfor receiving respective one bit lines of said bit line pairs from saidper-bit sensing circuits, and outputting data read to a selected one ofsaid bit line pairs; each of said per-bit sensing circuits comprising: apre-charge circuit connected to a corresponding one of said bit linepairs, for setting the corresponding one of said bit line pairs to apotential of a first power supply; a first latch circuit connected tothe corresponding one of said bit line pairs, for setting the other onebit line of the corresponding one of said bit line pairs to the firstsupply potential, when one bit line of the corresponding one of said bitline pairs is set to a second power supply potential; a second latchcircuit connected to the corresponding one of said bit line pairs, forassisting setting of the one bit line of the corresponding one of saidbit line pairs to the second power supply potential when the one bitline of the corresponding one of said bit line pairs is set to thesecond power supply potential; and a data write circuit connected to thecorresponding one of said bit line pairs, for receiving a write datasignal and setting the one bit line of the corresponding one of said bitline pairs to the second power supply potential according to value ofthe write data signal; wherein control of activation/deactivation of thepre-charge circuit, the data write circuit, and the second latch circuitis performed according to a bit line pair selection signal received. 7.The semiconductor storage device according to claim 6, wherein thepre-charge circuit comprises first and second MOS transistors of a firstconductivity type, with sources thereof connected in common to saidfirst power supply, drains thereof connected to the corresponding one ofsaid bit line pairs, respectively, and gates thereof connected to thebit line pair selection signal.
 8. The semiconductor storage deviceaccording to claim 6, wherein the first latch circuit comprises thirdand fourth MOS transistors of a first conductivity type, with sourcesthereof connected in common to said first power supply, drains thereofconnected to first and second bit lines constituting the correspondingone of said bit line pairs, respectively, and gates thereofcross-connected to the second and first bit lines, respectively.
 9. Thesemiconductor storage device according to claim 6, wherein the secondlatch circuit comprises: first and second MOS transistors of a secondconductivity type with drains thereof connected to first and second bitlines constituting the corresponding one of said bit line pairs,respectively, gates thereof cross-connected to the second and first bitlines, respectively, and sources thereof connected in common; and athird MOS transistor of a second conductivity type connected between acommon connecting node of the sources of the first and second MOStransistors and an inverted signal of a sensing circuit activationsignal, with a gate thereof connected to the bit line pair selectionsignal, for being subject to on/off control.
 10. The semiconductorstorage device according to claim 6, wherein the data write circuitcomprises: fourth and fifth MOS transistors of a second conductivitytype with drains thereof connected to first and second bit linesconstituting the corresponding one of said bit line pairs, respectively,and gates thereof connected to a pair of complementary write data signallines, respectively, and sources thereof connected in common; and asixth MOS transistor of said second conductivity type connected betweena common connecting node of the sources of the fourth and fifth MOStransistors and a second power supply potential, with a gate thereofconnected to the bit line pair selection signal, for being subject toon/off control.
 11. The semiconductor storage device according to claim9, wherein the second latch circuit comprises: a first MOS transistor ofsaid second conductivity type connected between a first bit lineconstituting the corresponding one of said bit line pairs and aninverted signal of a sensing circuit activation signal in series, with agate thereof connected to a second bit line of the corresponding one ofsaid bit line pairs; a third MOS transistor of said second conductivitytype with a gate thereof connected to the bit line pair selectionsignal, for being subject to on/off control; a second MOS transistor ofsaid second conductivity type connected in series between the second bitline and the inverted signal of the sensing circuit activation signal,with a gate thereof connected to the first bit line; and an eighth MOStransistor of said second conductivity type with a gate thereofconnected to the bit line pair selection signal, for being subject toon/off control.
 12. The semiconductor storage device according to claim6, wherein the data write circuit comprises: fourth and fifth MOStransistors of a second conductivity type connected in series between afirst bit line constituting the corresponding one of said bit line pairsand the second power supply potential; and sixth and seventh MOStransistors of said second conductivity type connected in series betweena second bit line constituting the corresponding one of said bit linepairs and the second power supply potential; gates of the fourth andsixth MOS transistors being connected to a pair of complementary writedata signal lines, respectively; the bit line pair selection signalbeing connected in common to gates of the fifth and seventh MOStransistors.
 13. The semiconductor storage device according to claim 6,wherein said data output circuit comprises: a logic circuit forreceiving respective one bit lines of said bit line pairs from saidper-bit sensing circuits, for outputting a first logic value when all ofthe bit lines received are at the first supply potential and outputtinga second logic value when at least one of the bit lines received is atthe second power supply potential; and an output transistor forreceiving an output signal of said logic circuit and driving a dataoutput line based on the output signal.
 14. The semiconductor storagecircuit according to claim 13, wherein said data output circuitcomprises an auxiliary circuit for receiving the sensing circuitactivation signal, and setting the inverted signal of the sensingcircuit activation signal to the second power supply potential when thesensing circuit activation signal is at the first supply potential. 15.The semiconductor storage device according to claim 13, wherein saidlogic circuit of said data output circuit comprises a plurality of fifthMOS transistors of said first conductivity type with gates thereofconnected to the plurality of bit lines, respectively, sources thereofconnected in common to said first power supply, and drains thereofconnected to one node; said data output circuit further comprisingseventh and eighth MOS transistors of said second conductivity typeconnected in parallel with each other between said one node and saidsecond power supply, with gate thereof connected to the inverted signalof the sensing circuit activation signal and to said data output line,respectively; said one node being connected to a gate of said outputtransistor with a source thereof grounded and a drain thereof connectedto said data output line.
 16. The semiconductor storage device accordingto claim 6, wherein the second latch circuit comprises: a first MOStransistor of a second conductivity type connected between a first bitline constituting the corresponding one of said bit line pairs and aninverted signal of a sensing circuit activation signal in series, with agate thereof connected to a second bit line of the corresponding one ofsaid bit line pairs; a third MOS transistor of said second conductivitytype with a gate thereof connected to the bit line pair selectionsignal, for being subject to on/off control; a second MOS transistor ofsaid second conductivity type connected between the second bit line andthe inverted signal of the sensing circuit activation signal, with agate thereof connected to the first bit line; and a fourth MOStransistor of said second conductivity type with a gate thereofconnected to the bit line pair selection signal, for being subject toon/off control.
 17. A semiconductor storage device comprising: a memorycell array including a plurality of memory cells respectively disposedat intersections between a plurality of bit line pairs and a pluralityof word lines disposed in a direction orthogonal to said bit line pairs;a plurality of per-bit sensing circuits connected to said plurality ofbit line pairs, respectively ; and a data output circuit for receivingrespective one bit lines of said bit line pairs from said per-bitsensing circuits, and outputting data read to a selected one of said bitline pairs; each of said per-bit sensing circuits comprising: apre-charge circuit comprising first and second MOS transistors of afirst conductivity type with sources thereof connected in common to afirst power supply, drains thereof connected to a corresponding one ofsaid bit line pairs, and gates thereof connected to a bit line pairselection signal; a first latch circuit comprising third and fourth MOStransistors of said first conductivity type with sources thereofconnected in common to said first power supply, drains thereof connectedto first and second bit lines constituting the corresponding one of saidbit line pairs, respectively, and gates thereof cross-connected to thesecond and first bit lines, respectively; a second latch circuitcomprising: first and second MOS transistors of a second conductivitytype with drains thereof connected to the first and second bit linesconstituting the corresponding one of said bit line pairs, respectively,gates thereof cross-connected to the second and first bit lines,respectively, and sources thereof connected in common; and a third MOStransistor of said second conductivity type connected between a commonconnecting node of the sources of the first and second MOS transistorsand an inverted signal of a sensing circuit activation signal, with agate thereof connected to the bit line pair selection signal, for beingsubject to on/off control; fourth and fifth MOS transistors of saidsecond conductivity type with drains thereof connected to the first andsecond bit lines constituting the corresponding one of said bit linepairs, respectively, gates thereof connected to a pair of complementarywrite data signal lines, respectively, and sources thereof connected incommon; and a data write circuit including a sixth MOS transistor ofsaid second conductivity type connected between a potential of a secondpower supply and a common connecting node of the sources of the firstand fifth MOS transistors, with a gate thereof connected to the bit linepair selection signal, for being subject to on/off control; said dataoutput circuit comprising: a logic circuit for outputting a first logicvalue when all of the bit lines from said per-bit sensing circuits areat the first supply potential and outputting a second logic value whenat least one of the bit lines is at the second power supply potential;and an output transistor for receiving an output signal of said logiccircuit and driving a data output line based on the output signal.
 18. Asemiconductor storage device comprising: a memory cell array including aplurality of memory cells disposed at intersections between a pluralityof bit line pairs and a plurality of word lines disposed in a directionorthogonal to said bit line pairs; a plurality of per-bit sensingcircuits connected to said plurality of bit line pairs, respectively ;and a data output circuit for receiving said respective bit line pairsof said per-bit sensing circuits and differentially outputting data readto a selected one of said bit line pairs; each of said per-bit sensingcircuits comprising: a pre-charge circuit comprising first and secondMOS transistors of a first conductivity type with sources thereofconnected in common to a first power supply, drains thereof connected toa corresponding one of said bit line pairs, and gates thereof connectedto the bit line pair selection signal; a first latch circuit comprisingthird and fourth MOS transistors of said first conductivity type withsources thereof connected in common to said first power supply, drainsthereof connected to first and second bit lines constituting thecorresponding one of said bit line pairs, respectively, and gatesthereof cross-connected to the second and first bit lines, respectively;a second latch circuit comprising: a first MOS transistor of a secondconductivity type with a drain thereof connected to the first bit line,a gate thereof connected to the second bit line, and a source thereofconnected to an inverted signal of a sensing circuit activation signalthrough a third MOS transistor of said second conductivity type with agate thereof connected to the bit line pair selection signal, for beingsubject to on/off control; and a second MOS transistor of said secondconductivity type with a drain thereof connected to the second bit line,a gate thereof connected to the first bit line, and a source thereofconnected to the inverted signal of the sensing circuit activationsignal through the third MOS transistor of said second conductivitytype; and a data write circuit including: a fourth MOS transistor ofsaid second conductivity type with a drain thereof connected to thefirst bit line, a gate thereof connected to one write data signal lineof a pair of complementary data signal lines, and a source thereofconnected to a second power supply potential through a sixth MOStransistor of said second conductivity type with a gate thereofconnected to the bit line pair selection signal, for being subject toon/off control; and a fifth MOS transistor of said second conductivitytype with a drain thereof connected to the second bit line, a gatethereof connected to the other write data signal line of the pair ofcomplementary write data signal lines, and a source thereof connected tothe second power supply potential through the sixth MOS transistor ofsaid second conductivity type; said data output circuit comprising: afirst logic circuit for receiving respective one bit lines of said bitline pairs from said plurality of per-bit sensing circuits, andoutputting a first logic value when all of the bit lines received are ata potential of said first power supply and outputting a second logicvalue when at least one of the bit lines received is at the second powersupply potential; a first output transistor for receiving an outputsignal of said first logic circuit and driving a first data output linebased on the output signal; a second logic circuit for receiving therespective other bit lines of said bit line pairs from said plurality ofper-bit sensing circuits, and outputting the first logic value when allof the bit lines received are at the first supply potential andoutputting the second logic value when at least one of the bit linesreceived is at the second power supply potential; and a second outputtransistor for receiving an output signal of said second logic circuitand driving a second data signal line complementary with said first dataoutput line, based on the output signal.
 19. The semiconductor storagedevice according to claim 18, wherein said data output circuit includesan auxiliary circuit for receiving the sensing circuit activationsignal, and setting the inverted signal of the sensing circuitactivation signal to the second power supply potential, when the sensingcircuit activation signal is at the first supply potential.
 20. Thesemiconductor storage device according to claim 18, wherein said dataoutput circuit comprises: a circuit for receiving the output signal ofsaid first logic circuit, for setting the output of said second logiccircuit to the second logic value when the output signal of said firstlogic circuit has the first logic value; and a circuit for receiving theoutput signal of said second logic circuit, for setting the outputsignal of said first logic circuit to the second logic value when theoutput signal of said second logic circuit has the first logic value.21. The semiconductor storage device according to claim 18, wherein saidfirst logic circuit of said data output circuit includes: a plurality offifth MOS transistors of said first conductivity type with gates thereofrespectively connected to each of one bit lines of said bit line pairs,sources thereof connected in common to said first power supply, anddrains thereof connected in common to a first node; said data outputcircuit further including seventh and eighth MOS transistor of saidsecond conductivity type connected between said first node and saidsecond power supply in parallel with each other, with a gate of saidseventh MOS transistor of said second conductivity type connected to theinverted signal of the sensing circuit activation signal; said firstnode being connected to a gate of said first output transistor with adrain thereof connected to said first data output line; and wherein saidsecond logic circuit of said data output circuit includes ninth MOStransistors of said first conductivity type with gates thereofrespectively connected to each of the other bit lines of said bit linepairs; sources thereof connected in common to said first power supply,and drains thereof connected in common to a second node; said dataoutput circuit further including tenth and eleventh MOS transistors ofsaid second conductivity type connected between said second node andsaid second power supply in parallel with each other, with a gate ofsaid tenth MOS transistor of said second conductivity type connected tothe inverted signal of the sensing circuit activation signal; saidsecond node being connected to a gate of said second output transistorwith a source thereof grounded, a drain thereof connected to a seconddata output line complementary with said first data output line; a gateof said eighth MOS transistor of said second conductivity type beingconnected to said second node; and a gate of said eleventh MOStransistor of said second conductivity type being connected to saidfirst node.
 22. The semiconductor storage device according to claim 18,wherein in the second latch circuit, the source of the first MOStransistor of said second conductivity type is connected to the invertedsignal of the sensing circuit activation signal through the third MOStransistor of said second conductivity type; and the source of thesecond MOS transistor of said second conductivity type is connected tothe inverted signal of the sensing circuit activation signal, through anMOS transistor of said second conductivity type provided aside from thethird MOS transistor of said second conductivity type, with a gatethereof connected to the bit line pair selection signal, for beingsubject to on/off control.
 23. The semiconductor storage deviceaccording to claim 18, in the data write circuit, the source of thefourth MOS transistor of said second conductivity type is connected tothe second power supply potential through the sixth MOS transistor ofsaid second conductivity type; and the source of the fifth MOStransistor of said second conductivity type is connected to the secondpower supply potential, through an MOS transistor of said secondconductivity type provided aside from the sixth MOS transistor of saidsecond conductivity type, with a gate thereof connected to the bit linepair selection signal, for being subject to on/off control.